As the need for greater processing capability in semiconductor devices increases, new methods for increasing performance of such devices have developed. One method involves merely increasing the device density on individual integrated circuit chips. Another involves arranging multiple integrated circuit chips on a planar surface, such as a printed circuit board. Recently, three-dimensional "stacking" has been proposed as a method for increasing the density and capability of semiconductor devices. Integrated circuit or chip "stacking" can be performed by grinding chip thickness to smaller dimensions (e.g., 100 .mu.m) and laminating multiple chips together into an electronic module or cube, as shown in FIG. 1.
One consequence of chip stacking is that unique wiring problems exist. Connection pads for each chip must be placed on the edge of the chip for electrical connections either to external devices or adjacent chips. FIG. 1 illustrates such an arrangement. Cube 10 consists of multiple, stacked integrated circuit chips 14. Bus and I/O network 12 can be arranged on a cube face with electrically conducting pads, e.g., 22a-22c providing the connection between interior chip devices and the bus and I/O network. For example, line 16 commonly connects a row of underlying pads. To connect interior chip devices, chip 14 employs metallization line 20 which is routed from the interior devices. The exposed edge of line 20 becomes pad 18 which provides a connection, through the bus and I/O network 12, to external devices or adjacent chips.
The pads are of necessarily small dimensions because they may be merely the exposed edge of a metallization line, and may be further constrained in size by the small chip edge on which they are mounted. Because of the small dimensions of such pads, unique alignment problems exist when placing a bus and I/O network over the pads. Specifically, lateral alignment and longitudinal spacing between pads on different chips must be controlled to enable the accurate placement of a bus and I/O network over the pads. In addition, requirements currently exist for very dense bus and I/O networks. The alignment and spacing of the pads will necessarily impact the accurate formation of dense bus and I/O networks.
FIG. 2 depicts an example of a bus and I/O network on a face of a module. Lateral alignment of pads 32a and 36a with pads 32b and 36b is required for line connections 30 and 34 which commonly connect all chips. In addition, some connections only require lines between pads on selected chips. For example, lines 38 and 42 require connections between pads 40a and 40b, and pads 44a and 44b, respectively. In such instances, longitudinal spacing between the pads must be accurately controlled to permit an accurate contact at, for instance, pad 44a.
Presently, lateral alignment between chips is performed by physically aligning the chip edges. The effectiveness of this physical alignment is impacted by (1) where the edge of each chip is defined which is created by the positioning of a mechanically aligned saw blade (used to dice the chips), and (2) the physical alignment mechanism that aligns one chip to another. Large line widths are often used to compensate for the large errors associated with physical alignment techniques. The alignment between pads chip-to-chip is therefore impacted by the positioning of a saw blade (and the associated large line widths used) and the variations in the physical alignment mechanism. Present capabilities offer saw blade tolerances of .+-.25 .mu.m and variances of .+-.71/2 .mu.m. Pad alignment chip-to-chip must take this into account as well as the variation of the physical alignment which is .+-.15 .mu.m.
Presently, control of longitudinal distances between each chip (and thus distances between pads on selected chips) is entirely dependent on the thickness of each chip. This thickness is determined during a grind stage in the fabrication process. For example, a physical reference is used to control a wafer grinder. The resultant thickness of a ground wafer cannot presently be adequately controlled with a physical reference to support the required wiring densities, as discussed above. Also, the glue layer required to laminate one chip to another can vary in its final thickness. Distances between stacked chips, and therefore between pads mounted thereon, will vary and impact the implementation of a dense bus and I/O network. This variance, using present technology, can be 20-30 .mu.m.
In U.S. Pat. No. 5,121,299 entitled "MULTILEVEL CIRCUIT STRUCTURE UTILIZING CONDUCTIVE CORES HAVING CONDUCTIVE PROTRUSIONS AND CAVITIES THEREIN," and assigned to the same assignee as the present invention, a technique is disclosed which provides precise registration (or lateral alignment) so that interconnections which are drilled through multiple layers will intersect at precise points. A system of protrusions and depressions is disclosed which provides the precise alignment, or registration. The protrusions and depressions are etched directly into the substrate. Etching the protrusions directly into the substrate requires a proportionately thicker substrate which in turn results in decreased electrical performance due to stray capacitances. In addition, there is no technique disclosed for precisely controlling the longitudinal distances between layers.
A need therefore exists for improved fabrication methods and resultant structures which will support cube arrangements, including dense bus and I/O networks placed thereon. Physical alignment through edge alignment or grinder control should be avoided. The resultant pad placement should be approximately as accurate as device placement within each chip, i.e., tolerances below 20 .mu.m. The alignment technique should also be independent of the thickness of the substrate thereby maintaining adequate electronic performance levels.